Which version of gcc
If in doubt, grab the latest you can - it tends to improve things.
and with what flags
This paper includes some useful instructions:
http://www.add.ece.ufl.edu/4924/docs/arm/ARM%20NEON%20Development.pdf
Is this gcc optimal?
No compiler ever produces optimal code for non-trivial examples. If in doubt look at the disassembly of what the compiler produces to check on what it is doing.
HTH,
Pete
Start with this ...
ARM Security Technology Building a Secure System using TrustZone Technology
HTH,
Pete
Hello, newbie right down to the socks here, but have to ask. From what I've seen most arm cpu/gpu are scaled to to what number of GPU it will use. I have a Allwinner A31S processor on a device that I know that should be Mali 400 MP4, but it instead its MP2 (Dual core). Is it possible to rescale a device to use its full potential? If so how?
Thanks in advance.
Hello and welcome,
Are you sure it is Mali inside?
It is a quad-core ARM Cortex-A7 Processor but I don't believe this particular Allwinner SoC features ARM Mali GPUs.
A31s_Allwinner Technology product page from Allwinner own website.
So, if it's a A31s, I don't think we can help you.
Cheers,
Alban
Hello,
>[This not specific to AXI3/4] Can someone give an example on how write data interleaving works?
Note that write data interleaving is only applicable to AXI3. There is no write data interleaving in AXI4.
Examples: see 1) 2) 3) below.
>Is it used only when we have multi-master cases?
No.
>or its possible with single-master cases also?
Yes.
>In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) then this can be interleaved as following
Let's assume that A is issued first. With that said:
>1) A1 B1 A2 B2 (interleaved)
This is legal.
>2) A1 A2 B1 B2 (In-order)
This is legal.
>3) B1 B2 A1 A2 (out of order)
This is illegal. AXI3 requires that the first WDATA item must be issued in the same order as the write address, regardless of the write ID. Since A is issued first in this example, A1 must occur first.
>....
Another legal example would be: A1 B1 B2 A2
>Please let me know if my understanding is not correct
>
>[AXI4] Do we support write out-of order write in AXI4? (I know that we removed WID signal from write data channel)
No. AXI4 has removed the support for write data interleaving. WID is removed in AXI4, so WDATA must strictly follow the AW order.
>In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave?
First of all, an AXI4 master must not issue interleaved write data.
Secondly, the interconnect must ensure that write data is not interleaved when merging data streams from different masters to the same slave.
Regards,
Xingguang
Any further news on the r4p0 userspace drivers?
Any further news on the r4p0 userspace drivers?
Hi Nishad - You'll probably find this thread useful AAME Certification Preparation Suggestions
Best of luck!
Hello,
I'm sorry for asking such a generic question but I have been reading up about this for the past week or so and haven't really gotten anywhere. I'm an embedded developer working with ARM and AVR devices for the past 2-3 years. So I am quite comfortable working with embedded systems.
Recently I have been reading up on a lot of IoT stuff and have managed to cover the following :
Some of the IoT protocols (CoAP,MQTT,DTLS/UDP,REST)
Some IoT platforms and libraries (Erbium CoAP library, Contiki OS)
Cloud Services
I haven't read all of these in detail but I now have a general idea of how they work and where they fit in.
However I am still not able to get a proper picture of how an IoT system would compare with a traditional system, and what would be the different design principles while setting about designing such a system. If any of you could point me towards some articles or other material which would help me get a better direction I would be very grateful.
Also,I have seen in the past that the best way to learn these things is to do. So could any of you suggest some simple projects I could work on so that I would get a better idea of the IoT infrastructure? (P.S. I am new to web development and web services but would love to be able to code for all the layers as I always like learning new things)
Thanks
Nishad
Hi Nishad,
You're in luck! We've had quite a few elements posted about that lately:
If you search the community for nanoservice, or coap, you will find additional content.
I'd recommend you start with the tutorial though, as it doesn't only talk about CoAP, but also explains other aspects like the REST principles.
Greetings ARM community,
I have been tasked with cache maintenance. The necessity popped up because of DMA issues on USB.
As a quick (not perm solution) I used the invalidate all routine. While obviously not nominal in anyway
it does allow me to continue with USB tasks.
This is the assy for that. Pretty common example from the Cortex R4 and ARM ARM.
MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register configuration data
DSB 0x0f
MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
ISB 0x0f
BX lr
ENDFUNC
Moving forward I am trying to implement the invalidation by MVA to PoC and having no luck. This is my first go at this so it more than likely my misunderstanding which command to use.
If I can ask; which invalidate by MVA should I be using? Is their a paper or section of the document arm arm to point it out?
The memory is configured as write-through.
I am going to experiment more with the other MVA to UoC but I want to gain a better understanding of this.
Is there any example code of going from AArch64 EL3 to AArch32 EL1? I'm trying to do this now with code similar to this, but I am aborting because the CPSR is incorrect after the eret.
mrs x0, currentel
cmp x0, #0xc
b.ne br_to_test
mov x0, #0x030 // RES1 field
tst x26, #0x1 // do we switch to 32-bit for lower EL's?
beq 1f
orr x0, x0, #0x400 // Lower EL's are AArch64
1:
orr x0, x0, #0x100 // HVC instruction enabled
msr scr_el3, x0
msr cptr_el3, xzr // don't trap to EL3
msr sctlr_el2, xzr
// setup some EL2 stuff
tst x26, #0x1 // do we switch to 32-bit for lower EL's?
beq 1f
mrs x0, hcr_el2
orr x0, x0, #(1 << 31) // 64-bit EL1
msr hcr_el2, x0
1:
msr ttbr0_el2, xzr // clear out the page table address for EL2
// Coprocessor traps.
mov x0, #0x33ff
msr cptr_el2, x0 // Disable copro. traps to EL2
msr hstr_el2, xzr // Disable CP15 traps to EL2 in AArch32
// now go to EL1 with eret
ldr w0, [x29, #0] // next image address
tst x26, #0x1
b.eq 1f // need to setup for 32-bit
mov x1, #0x3c5 // AArch64 - EL1h + D,A,I,F disabled
b 2f
1: mov x1, #0x10 // AArch32 - Supervisor + D,A,I,F disabled
2: msr elr_el3, x0
msr spsr_el3, x1
eret
Hi,
I'm working with gem5 simulator to model a dual cluster system, which has two aarch64 CPU model
Is there CCI-400 model for gem5? or How can I model a snoopable system bus with gem5?
Hayoung Jeong
An example would be something like this....
; Put SCTLRs for lower ELs into known state MSR SCTLR_EL2, XZR MSR SCTLR_EL1, XZR MSR SCR_EL3, XZR ; NS=0 (secure), RW=0 (next EL down is AArch32), SMD=0 (SMCs enabled), IRQ/FIQ=0 (not routed to EL3) ADR x1, <label in EL1> MSR ELR_EL3, x1 MOV x1, #0x13 (AArch32 SVC mode) MSR spsr_el3, x1 ERET
Are you also using the ISSM in RVDS?
It'll depend on exactly what you're doing. Given that you're interacting with a DMA, I would expect you use one of the operations to PoC (Point of Coherency). That would be DCCMVAC (clean), DCIMVAC (invalidate) or DCCIMVAC (clean & invalidate).
Getting the correct barriers in place for cache maintenance routines can be tricky. If it's something your unfamiliar with I'd recommend reading the Barrier Litmus Tests appendix of the ARM Architecture Reference Manual.
The ARM Compiler 6 tool chain is based on LLVM, but currently that is aimed at ARMv8-A:
http://ds.arm.com/ds-5/build/arm-compiler-6/
I've not used the trunk version of LLVM, but looking at the Release Notes (LLVM 3.5 Release Notes — LLVM 3.4 documentation) the support seems to be there as well.
Wow ... thank you Brad.
I work in Marin County though, so unfortunately I can't get to your office today.
Is there any way you could leave it at will call tomorrow?
I'm sure you guys have a million things going on so if you can't leave it at
will call I totally understand.
Either way I look forward to stopping by your booth tomorrow.
Thanks.
- Joel
Hi there,
I have question regarding handshaking in the AXI protocol.Currently i am designing decorder for AXI4-Lite master .
While doing the write adress transaction, AWVALID depends upon write enable.AWVALID is high when write enable signal is high. AWREADY from slave is default HIGH so transaction happens in one clock. After the completion of transaction , AWVALID check for AWREADY HIGH and sets AWVALID low in next clock.
I am confused if this is the valid way of doing transaction because AXI specs says VALID signal must not depend upon READY signal.
Hi Joel - I just spoke with our Events team and unfortunately they are not able to handle your request. Apologies it didn't work out, but have a great time!
